US 2011/0238890 A1 · MEMORY CONTROLLER, MEMORY SYSTEM, PERSONAL COMPUTER, AND METHOD OF CONTROLLING MEMORY SYSTEM

Abstract

According to one embodiment, a memory controller that performs control of a nonvolatile semiconductor memory includes a first management table that stores correspondence between logical block addresses and physical block addresses, a second management table that stores a number of times of data writing for each of the logical block addresses, and a third management table that stores a number of times of data erasing for each of the physical block addresses. The memory controller according to the embodiment includes a writing control unit that selects a spare block not associated with the logical block address and writes data in the spare block. The writing control unit levels, based on the number of times of data writing associated with the logical block addresses and the number of times of data erasing associated with the physical block addresses, numbers of times of data erasing among the blocks.

Claims21

Dependent claims

A memory controller that performs control of a nonvolatile semiconductor memory including a plurality of blocks, the block being a unit of data erasing, the memory controller comprising:

a first management table that stores correspondence between logical block addresses and physical block addresses;
a second management table that stores a number of times of data writing for each of the logical block addresses;
a third management table that stores a number of times of data erasing for each of the physical block addresses;
and
a writing control unit that selects a spare block not associated with the logical block address and writes data in the spare block, wherein
the writing control unit levels, based on the number of times of data writing associated with the logical block addresses and the number of times of data erasing associated with the physical block addresses, numbers of times of data erasing among the blocks.

3 more elements

A memory system comprising:

a nonvolatile semiconductor memory having a plurality of blocks as units of data erasing;
and
a memory controller that performs control for rewriting data of the nonvolatile semiconductor memory, the memory controller including:
a first management table that stores correspondence between logical block addresses as logical addresses in the block units designated by a host and physical block addresses indicating storage locations in the nonvolatile semiconductor memory of the blocks;
a second management table that stores, for each of the logical block addresses, a number of times of writing of data in the nonvolatile semiconductor memory from the host;
a third management table that stores a number of times of data erasing for each of the physical block addresses;
and
a writing control unit that selects, in response to a writing request designating a logical address from the host, a spare block as the block not having logical address corresponding thereto and writes data in the spare block, wherein
the memory controller averages, based on the number of times of writing of data stored for each of the logical block addresses and the number of times of data erasing stored for each of the physical block addresses, numbers of times of data erasing among the blocks.

6 more elements

A method of controlling a memory system including a nonvolatile semiconductor memory having a plurality of blocks, the block being a unit of data erasing, and a memory controller that performs control of the nonvolatile semiconductor memory, the method comprising the memory controller storing, in a first management table, correspondence between logical block addresses and physical block addresses, storing, in a second management table, a number of times of data writing for each of the logical block addresses, and storing, in a third management table, a number of times of data erasing for each of the physical block addresses, wherein

writing control for selecting a spare block not associated with the logical address and writing data in the spare block includes leveling, based on the number of times of data writing associated with the logical block addresses and the number of times of data erasing associated with the physical block addresses, numbers of times of data erasing among the blocks.

Dependencies are inferred from the claim text.

Memory controller, memory system, personal computer, and method of controlling memory system

Life of this patent

Memory controller, memory system, personal computer, and method of controlling memory system

Life of this patent

Abstract

Claims21