Information processing device

An information processing device comprising:

• a CPU operable to issue a bus command for commanding a bitwise write operation when executing a fetched command;
• and
• a peripheral module coupled to the CPU via a bus,
• wherein the peripheral module comprises:
• a register rewritable by the CPU;
• and
• a bit operation controller operable to execute a bitwise write operation to the register, in response to the bus command.

An information processing device comprising:

• a CPU operable to issue a first bus command for commanding a bitwise write operation when executing a fetched command;
• a peripheral module coupled to the CPU via a bus;
• and
• a bus state controller coupled to the bus and operable to perform bus state control,
• wherein the bus state controller comprises:
• a first circuit operable to make a distinction of whether the peripheral module supports the bus command;
• a second circuit operable to convert the first bus command issued by the CPU into a second bus command supported by the peripheral module;
• and
• a third circuit operable to output to the peripheral module selectively the first bus command transferred from the CPU and the second bus command outputted by the second circuit, based on the distinction made by the first circuit.