US 2011/0237030 A1Published application

Die level integrated interconnect decal manufacturing method and apparatus

AssigneeInternational Business Machines Corporation

InventorsPeter A. Gruber, Jae-Woong Nah

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Abstract

A die level integrated interconnect decal manufacturing method and apparatus for implementing the method. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

Claims18

Dependent claims

A method of producing die level interconnect decals, said method comprising the steps of:

(a) providing a plurality of superimposed apertured decals, said plurality of decals including an upper layer having alignment holes and tapered feature holes, a center layer having arrays of through features holes in alignment with said tapered feature holes and in alignment with through feature holes in a bottom layer located on an opposite side of said layer;
a plurality of perforations extending through said center layer defining specific areas encompassing said arrays of feature holes;
(b) forming alignment holes in said center layer in alignment with alignment holes in said bottom layer arranged about the peripheries of said layers for maintaining said layers in aligned relationship;
(c) positioning a carrier stage having a substrate located thereon beneath said bottom layer, said carrier having upstanding pin numbers extending through the alignment holes in said upper, bottom and center layers;
(d) filling the feature holes in said decal layers with molten solder and cooling said solder;
(e) peeling said upper and bottom layers from said center layer and applying an adhesive layer to the exposed surface of said center layer encompassing solder portions projecting therefrom,
(f) mounting semiconductor chips on at least one said exposed surface of the center layer, in alignment with the areas defined by said perforations and in contact with said adhesive and solder portions;
(g) separating said semiconductor chips with the adherent solder-filled center layer along the areas bounded by said perforations from the remainder of said center layer, and
(h) withdrawing said carrier stage while enabling said substrate to remain adhesively adherent to the adhesive layer in contact with the solder portion projecting from the lower surface of said center layer.

6 more elements

An apparatus for providing electronic packages including die level interconnect decals, comprising:

(a) an arrangement for supplying a plurality of superimposed apertured decals, said plurality of decals including an upper layer having alignment holes and tapered feature holes, a center layer having arrays of through features holes and in alignment with said tapered feature holes and in alignment with through feature holes in a bottom layer located on an opposite side of said layer;
a plurality of perforations extending through said center layer defining specific areas encompassing said arrays of feature holes;
and alignment holes in said center layer in alignment with alignment holes in said bottom layer arranged about the peripheries of said layers for maintaining said layers in aligned relationship;
(b) a carrier stage having a substrate located thereon being located beneath said bottom layer, said carrier having upstanding pin numbers extending through the alignment holes in said upper, bottom and center layers;
(c) an arrangement for filling the feature holes in said decal layers with molten solder and cooling said solder;
(d) a device for separating said upper and bottom layers from said center layer and for applying an adhesive layer to the exposed surfaces of said center layer encompassing solder portions projecting therefrom;
(e) a device for positioning semiconductor chips on at least the exposed upper surface of said center layer in alignment with the areas defined by said perforations and in contact with said adhesive and exposed solder portions;
(f) a separating structure for detaching said semiconductor chips with the adherent solder-filled center layer along the areas bounded by perforations from the remainder of said center layer, and
(h) a device for withdrawing said carrier stage while said substrate remains adhesively adherent to the adhesive layer in contact with the solder portion projecting from the lower surface of said center layer.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/731,802Filed 25 Mar 2010
Published: 29 Sep 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification33 codes

H10W 70/635
Vias, e.g. via plugs: through-vias
H10W 70/095
Of insulating or insulated package substrates, or of interposers, or of redistribution layers: of vias therein
H10W 72/0113
Apparatus therefor: apparatus for manufacturing die-attach connectors
H10W 72/013
Manufacture or treatment: of die-attach connectors

Family

US 8,053,283 B2Related patent
US 2011/0237030 A1This patent

From the US filing history. Foreign family members aren’t listed.

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