US 2011/0235444 A1Published application

Sram writing system and related apparatus

AssigneeFaraday Technology Corp.

InventorsChing-Te Chuang, Wei-Chiang Shih, Hung-Yu Lee, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Kun-Di Lee

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Abstract

SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

Claims16

Dependent claims

An SRAM writing system comprising:

a dummy replica writing circuit corresponding to at least a dummy replica write bit-line, driving a level transition of the dummy replica write bit-line;
a negative pulse controller coupled to the dummy replica write bit-line, generating a negative pulse control signal according to level of the dummy replica write bit-line;
and
at least a normal writing circuit, each normal writing circuit corresponding to at least a normal write bit-line and comprising:
a write driver with a bias node;
the write driver connecting the corresponding normal write bit-line to level of the bias node for driving a level transition of the corresponding normal write bit-line;
and
a negative pulse supplier coupled to the bias node, alternately connecting the bias node to one of an operation voltage and a negative pulse voltage according to level of the negative pulse control signal;
wherein the operation voltage and the negative pulse voltage are different.

6 more elements

An SRAM comprising:

a dummy replica writing circuit corresponding to at least a dummy replica write bit-line, driving a level transition of the dummy replica write bit-line;
a negative pulse controller coupled to the dummy replica write bit-line, generating a negative pulse control signal according to level of the dummy replica write bit-line;
and
at least a normal writing circuit, each normal writing circuit corresponding to at least a normal write bit-line and comprising:
a write driver with a bias node;
the write driver connecting the corresponding normal write bit-line to a level of the bias node for driving a level transition of the corresponding normal write bit-line;
and
a negative pulse supplier coupled to the bias node, alternately connecting the bias node to one of an operation voltage and a negative pulse voltage according to level of the negative pulse control signal;
wherein the operation voltage and the negative pulse voltage are different.

6 more elements

Dependencies are inferred from the claim text.