US 2011/0235424 A1 · HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY

Abstract

Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.

Claims15

Dependent claims

A NAND Flash memory device comprising:

a NAND Flash cell block including a plurality NAND flash memory strings connected to a local common source line, and
a local switch logic including:
a first semiconductor switch for selectively allowing passage of a signal received on a global common source line to the cell block on the local common source line;
and
a second semiconductor switch for selectively placing a predetermined voltage on the local common source line.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/154,891Filed 7 Jun 2011

Priority

21 Dec 2007

Published

29 Sep 2011

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 16/3427
Disturbance prevention or evaluation; Refreshing of disturbed memory data: circuits or methods to prevent or reduce disturbance of the state of a…
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/12
Programming or data input circuits: programming voltage switching circuits
G11C 16/30
Auxiliary circuits, e.g. for writing into memory: power supply circuits

Family

Application61/015,909Us provisional application · filed 21 Dec 2007

Application12/337,038Continuation · filed 17 Dec 2008

Application13/154,891Continuation

US 2009/0161437 A1Published application

US 7,978,518 B2Related patent

US 8,208,306 B2Related patent

US 2011/0235424 A1This patent

From the US filing history. Foreign family members aren’t listed.

Hierarchical common source line structure in nand flash memory

Life of this patent

Hierarchical common source line structure in nand flash memory

Life of this patent

Abstract

Claims15