Nonvolatile semiconductor memory device and method of controlling nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device, comprising:

• a memory cell array configured as an array of a plurality of memory strings each including a plurality of memory cells connected in series, each of the memory cells being caused to store first to fourth data by being provided with a first threshold voltage distribution, a second threshold voltage distribution having a voltage value higher than that of the first threshold voltage distribution, a third threshold voltage distribution having a voltage value higher than that of the second threshold voltage distribution, or a fourth threshold voltage distribution having a voltage value higher than that of the third threshold voltage distribution;
• and
• a control circuit configured to be able to execute first page writing to shift a threshold voltage of the memory cell from the first threshold voltage distribution to an intermediate distribution, and second page writing to shift a threshold voltage of the memory cell from the first threshold voltage distribution to the second threshold voltage distribution or from the intermediate distribution to the third or fourth threshold voltage distribution, and configured to be able to execute reading of data from a reading target, which is a first memory cell among the plurality of memory cells, by applying to the first memory cell any one of reading voltages each having a voltage value between adjoining two of the first to fourth threshold voltage distributions, while applying a first reading pass voltage higher than an upper limit of the fourth threshold voltage distribution to other memory cells,
• the control circuit being configured to set a lower limit of the intermediate distribution in the first page writing such that an amount of shift from the first threshold voltage distribution to the second threshold voltage distribution is substantially equal to an amount of shift from the intermediate distribution to the fourth threshold voltage distribution,
• the control circuit being configured to, when a threshold voltage distribution of a second memory cell adjoining the first memory cell and subject to data write after the first memory cell is the second or fourth threshold voltage distribution, execute control of applying a second reading pass voltage higher than the first reading pass voltage to the second memory cell.

A method of controlling a nonvolatile semiconductor memory device,

• the nonvolatile semiconductor memory device comprising a memory cell array configured as an array of a plurality of memory strings each including a plurality of memory cells connected in series, each of the memory cells being caused to store first to fourth data by being provided with a first threshold voltage distribution, a second threshold voltage distribution having a voltage value higher than that of the first threshold voltage distribution, a third threshold voltage distribution having a voltage value higher than that of the second threshold voltage distribution, or a fourth threshold voltage distribution having a voltage value higher than that of the third threshold voltage distribution,
• in a data writing operation, the method comprising:
• executing first page wiring to shift a threshold voltage of the memory cell from the first threshold voltage distribution to an intermediate distribution;
• executing second page writing to shift the threshold voltage of the memory cell from the first threshold voltage distribution to the second threshold voltage distribution, or from the intermediate distribution to the third or fourth threshold voltage distribution to set a lower limit of the intermediate distribution in the first page writing such that an amount of shift from the first threshold voltage distribution to the second threshold voltage distribution is substantially equal to an amount of shift from the intermediate distribution to the fourth threshold voltage distribution, and
• in a data reading operation, the method comprising:
• applying to a reading target first memory cell among the plurality of memory cells any one of reading voltages each having a voltage value between adjoining two of the first to fourth threshold voltage distributions, and applying a first reading pass voltage higher than an upper limit of the fourth threshold voltage distribution to other memory cells;
• and
• when a threshold voltage distribution of a second memory cell adjoining the first memory cell and having data written thereinto after the first memory cell is the second or fourth threshold voltage distribution, applying a second reading pass voltage higher than the first reading pass voltage to the second memory cell.