Semiconductor memory device and a method of manufacturing the same

A semiconductor memory device, comprising:

• a substrate including first, second and third well regions, wherein the first well region is disposed between the second and third well regions, the first well region includes a first type conductor and the second and third well regions each include a second type conductor;
• a first active region that is included in the first well region, wherein first and second pull-up devices are disposed in a line in the first active region;
• a second active region that is included in the second well region, wherein a first access device and a first pull-down device are disposed in the second active region, the first access device is disposed adjacent to the second pull-up device and the first pull-down device is disposed adjacent to the first pull-up device;
• and
• a third active region that is included in the third well region, wherein a second access device and a second pull-down device are disposed in the third active region, the second access device is disposed adjacent to the first pull-up device and the second pull-down device is disposed adjacent to the second pull-up device.

A semiconductor memory device, comprising:

• a substrate including first, second and third well regions, wherein the first well region is disposed between the second and third well regions, the first well region includes a first type conductor and the second and third regions each include a second type conductor;
• first and second pull-down devices disposed in a line in the first well region and sharing a ground voltage terminal;
• a first pull-up device disposed in the second well region, wherein the first pull-up device is adjacent to the first pull-down device;
• a second pull-up device disposed in the third well region, wherein the second pull-up device is adjacent to the second pull-down device;
• a first access device disposed in the second well region, wherein the first access device is adjacent to the second pull-down device;
• and
• a second access device disposed in the third well region, wherein the second access device is adjacent to the first pull-down device.

A semiconductor memory device, comprising:

• a substrate including first, second and third well regions, wherein the first well region is disposed between the second and third well regions, the first well region includes a first type conductor and the second and third well regions each include a second type conductor;
• a first active region that is included in the first well region, wherein first and second pull-down devices are disposed in a line in the first active region;
• a second active region that is included in the second well region, wherein a first access device and a first pull-up device are included in the second active region, the first access device is disposed adjacent to the second pull-down device and the first pull-up device is disposed adjacent to the first pull-down device;
• and
• a third active region that is included in the third well region, wherein a second access device and a second pull-up device are included in the third active region, the second access device is disposed adjacent to the first pull-down device and the second pull-up device is disposed adjacent to the second pull-down device.

A semiconductor memory device, comprising:

• a substrate including first, second and third well regions, wherein the first well region is disposed between the second and third well regions, the first well region includes a first type conductor, and the second and third well regions each include a second type conductor, and
• wherein the first well region includes a first stacked structure, the first stacked structure including a first contact plug, a first metallic insulating layer, a via plug and a power supply or ground voltage line sequentially stacked on a first single active layer;
• the second well region includes a second stacked structure, the second stacked structure including a second contact plug and a second metallic insulating layer sequentially stacked on a second single active layer;
• and
• the third well region includes a third stacked structure, the third stacked structure including a third contact plug and a third metallic insulating layer sequentially stacked on a third single active layer.