Semiconductor memory device and method for controlling the same

A semiconductor memory device comprising:

• a memory cell array in which a group of memory cells each comprising a variable-resistance element is arranged;
• a voltage generation circuit configured to generate at least a write voltage for the memory cell array;
• and
• a control circuit configured to determine a select bit number for the memory cell group, set a write voltage corresponding to the select bit number, apply the set write voltage to the memory cell group, perform verify read on the memory cell group to which the write voltage has been applied to determine whether or not all of the select bits pass the verify read, and upon determining that not all the select bits successfully pass the verify read, control the memory cell array and the voltage generation circuit so that the number of passed bits is subtracted from the select bit number to set again a first voltage corresponding to the decreased select bit number.