Semiconductor memory device and writing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsShigeki KOBAYASHI, Kazuhiko Yamamoto
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AssigneeKabushiki Kaisha Toshiba
InventorsShigeki KOBAYASHI, Kazuhiko Yamamoto
Estimating the term…
A memory cell array includes memory transistors each including a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a variable resistance film formed on the gate electrode and made of a variable resistance material having variable resistance and is configured by plural memory strings disposed with longer direction extending in a first direction and including plural series-connected memory transistors. Word lines are disposed with a longer direction extending in a second direction orthogonal to the first direction, and connected commonly to the gate electrodes of the plural memory transistors lined up in the second direction. A plate line is disposed to sandwich the variable resistance film with the gate electrode. First voltage terminals supply a certain voltage to first ends of the plural memory strings. Second voltage terminals supply a certain voltage to second ends of the plural memory strings.
A semiconductor memory device, comprising:
A writing method of a semiconductor memory device, the semiconductor memory device comprising:
Dependencies are inferred from the claim text.