US 2011/0235389 A1 · SEMICONDUCTOR DEVICE

Abstract

An object is reduction in power consumption of a semiconductor device including a memory circuit. In the semiconductor device including a memory circuit, the memory circuit includes a memory cell including a semiconductor element and a memory cell that does not include a semiconductor element in a region defined by a word line and a bit line which intersect with each other. A transistor formed using an oxide semiconductor so as to have extremely low off-state current is used as the semiconductor element, so that the reading precision is improved and thus low voltage operation can be performed. The memory cells store data high or data low. The memory cell comprising a semiconductor element stores minor data of high and low, and the memory cell that does not comprise the semiconductor element stores major data of high and low.

Claims18

Dependent claims

A semiconductor device comprising:

a central processing unit;
and
a memory circuit comprising:
a first memory cell defined by a first bit line and a first word line intersecting with each other;
and
a second memory cell defined by a second bit line and a second word line intersecting with each other,
wherein the first memory cell comprises a first transistor,
wherein the second memory cell does not comprise a semiconductor element,
wherein the first transistor comprises an oxide semiconductor in a channel formation region,
wherein a gate of the first transistor is electrically connected to the first word line, a drain of the first transistor is electrically connected to the first bit line, and a source of the first transistor is electrically connected to a reference potential line,
wherein the memory circuit stores data of a program, and
wherein the central processing unit is configured to execute an operation based on the program.

9 more elements

A semiconductor device comprising:

a dedicated circuit;
and
a memory circuit comprising:
a first memory cell defined by a first bit line and a first word line intersecting with each other;
and
a second memory cell defined by a second bit line and a second word line intersecting with each other,
wherein the first memory cell comprises a first transistor,
wherein the second memory cell does not comprise a semiconductor element,
wherein the first transistor comprises an oxide semiconductor in a channel formation region,
wherein a gate of the first transistor is electrically connected to the first word line, a drain of the first transistor is electrically connected to the first bit line, and a source of the first transistor is electrically connected to a reference potential line,
wherein the memory circuit stores data of a program, and
wherein the dedicated circuit is configured to execute an arithmetic operation based on the program.

9 more elements

A semiconductor device comprising:

a central processing unit;
a dedicated circuit;
and
a memory circuit comprising:
a first memory cell defined by a first word line and a first bit line intersecting with each other;
and
a second memory cell defined by a second word line and a second bit line intersecting with each other,
wherein the first memory cell comprises a first transistor,
wherein the second memory cell does not comprise a semiconductor element,
wherein the first transistor comprises an oxide semiconductor in a channel formation region,
wherein a gate of the first transistor is electrically connected to the first word line, a drain of the first transistor is electrically connected to the first bit line, and a source of the first transistor is electrically connected to a reference potential line,
wherein the memory circuit stores data of a program,
wherein the central processing unit is configured to execute an operation based on the program, and
wherein the dedicated circuit is configured to execute an arithmetic operation based on the program.

11 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims18