Shift register with low power consumption

A liquid crystal display (LCD), comprising:

• (a) a liquid crystal panel having a plurality of pixels spatially arranged in the form of a matrix;
• (b) a plurality of scanning lines spatially arranged along a row direction, wherein each two neighboring scanning lines define a pixel row therebetween;
• and
• (c) a gate driver adapted for generating a plurality of gate signals for driving the plurality of pixels, wherein the gate driver comprises a shift register having a plurality of stages, {Sn}, connected in serial, n=1, 2, . . . , N, N being a positive integer, wherein each stage Sn comprises:
• (i) a first output electrically coupled a corresponding gate line for outputting a gate signal, G(n), thereto;
• (ii) a pull-up circuit electrically coupled between a node, Q(n), and the second output;
• (iii) a pull-up control circuit electrically coupled to the node Q(n);
• (iv) a pull-down circuit electrically coupled between the node Q(n) and the first output;
• and
• (v) a control circuit electrically coupled between the node Q(n) and the first output.

The LCD of claim 13, wherein the pull-down circuit comprises a pull-down control circuit comprises a first pull-down control circuit and a second pull-down control circuit, wherein each of the first and second pull-down control circuits comprises:

• (a) a first transistor T51/T61 having a gate configured to receive a first clock signal, LC1 or a second clock signal, LC2, a source electrically coupled to the gate and a drain;
• (b) a second transistor T52/T62 having a gate electrically coupled to the node Q(n), a source electrically coupled to the drain of the first transistor T51/T61 and a drain configured to receive a supply voltage VSS;
• (c) a third transistor T53/T63 having a gate electrically coupled to the drain of the first transistor T51/T61, a source electrically coupled to the source of the first transistor T51/T6 and a drain electrically coupled to a node P(n)/K(n);
• and
• (d) a four transistor T54/T64 having a gate electrically coupled to the node Q(n), a source electrically coupled to the drain of the third transistor T53/T63 and a drain configured to receive a supply voltage VSS.

The LCD of claim 14, wherein the pull-down circuit further comprises a first pull-down circuit and a second pull-down circuit, wherein the first pull-down circuit comprises:

• (a) a first transistor T31 having a gate electrically coupled to the node P(n) of the first pull-down control circuit, a source electrically coupled to the node Q(n) and a drain electrically coupled to the first output;
• and
• (b) a second transistor T32 having a gate electrically coupled to the node P(n) of the first pull-down control circuit, a source electrically coupled to the first output and a drain configured to receive the supply voltage VSS;
• and
• wherein the second pull-down circuit comprises:
• (i) a first transistor T41 having a gate electrically coupled to the node K(n) of the second pull-down control circuit, a source electrically coupled to the node Q(n) and a drain electrically coupled to the first output;
• and
• (ii) a second transistor T42 having a gate electrically coupled to the node K(n) of the second pull-down control circuit, a source electrically coupled to the first output and a drain configured to receive the supply voltage VSS;
• (iii) a third transistor T43 having a gate electrically coupled to the second output of the stage Sn+1, a source electrically coupled to the node Q(n) and a drain configured to receive the supply voltage VSS;
• and
• (iv) a fourth transistor T44 having a gate electrically coupled to the second output of the stage Sn+1, a source electrically coupled to the first output and a drain configured to receive the supply voltage VSS.