Using end-to-end credit flow control to reduce number of virtual lanes implemented at link and switch layers

A circuit for implementing transport layer flow control in an interconnect system comprising:

• a transport layer;
• an application layer coupled to said transport layer;
• a respective switch and link layer coupled to said transport layer;
• said transport layer supporting multiple virtual lanes to said application layer, and providing buffering and credit control for said multiple virtual lanes;
• a source transport layer, sending a credit request message for a virtual lane to a destination transport layer;
• and
• said source transport layer, sending a packet from the virtual lane to said destination transport layer only responsive to the credit request being granted by said destination transport layer.

A multiple-path local rack interconnect system comprising:

• a plurality of interconnect chips;
• a plurality of serial links connected between each of said plurality of interconnect chips;
• each of said interconnect chips including a transport layer;
• an application layer coupled to said transport layer;
• a respective switch and link layer coupled to said transport layer;
• said transport layer supporting multiple virtual lanes to said application layer, and providing buffering and credit control for said multiple virtual lanes;
• a source transport layer, sending a credit request message for a virtual lane to a destination transport layer;
• and
• said source transport layer, sending a packet from the virtual lane to said destination transport layer only responsive to the credit request being granted by said destination transport layer.

A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

• a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing transport layer flow control in an interconnect system, said circuit comprising:
• a transport layer;
• an application layer coupled to said transport layer;
• a respective switch and link layer coupled to said transport layer;
• said transport layer supporting multiple virtual lanes to said application layer, and providing buffering and credit control for said multiple virtual lanes;
• a source transport layer, sending a credit request message for a virtual lane to a destination transport layer;
• and
• said source transport layer, sending a packet for the virtual lane to said destination transport layer only responsive to the credit request being granted by said destination transport layer, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.