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US 2011/0216454 A1Published application
Electrostatic discharge protectors having increased rc delays
AssigneeMacronix International Co., Ltd.
InventorsShih-Yu Wang, Chia-Ling Lu, Yu-Lien Liu, Yan-Yu Chen, Che-Shih Lin, Tao-Cheng Lu
Life of this patent
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Abstract
An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.
Claims20
A delay circuit for an electrostatic discharge (ESD) protector, comprising:
- a capacitor having a terminal connected to a node;
- a first transistor having a drain terminal connected to the node;
- and
- a second transistor having a drain terminal connected to a gate terminal of the first transistor and a gate terminal connected to the node.
1 more element
A delay circuit arrangement, comprising:
- a capacitor having a terminal connected to an output voltage line;
- first and second transistors connected together by way of their drain and gate terminals, respectively, being connected to the output voltage line;
- and
- an electrostatic discharge (ESD) protector coupled to the output voltage line.
1 more element
A method for providing electrostatic discharge (ESD) protection, comprising:
- providing a capacitor, a first transistor, a second transistor, and an ESD protector;
- coupling a terminal of the capacitor, a drain terminal of the first transistor and a gate terminal of the second transistor together to form a node;
- connecting a gate terminal of the first transistor to a drain terminal of the second transistor, whereby the capacitor, the first transistor and second transistor are formed into a delay circuit;
- and
- coupling the node of the delay circuit to the electrostatic discharge (ESD) protector.
2 more elements
Dependencies are inferred from the claim text.