DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER

A data-path cell produced on a semiconductor-on-insulator substrate comprising a thin layer of semiconductor material separated from a bulk substrate by an insulating layer, the cell comprising an array of field-effect transistors (FETs), each transistor comprising:

• in the thin layer of semiconductor material, a source region, a drain region and a channel region interposed between the source and drain regions,
• above the channel region, a front gate control region;
• and
• one or more back gate control regions formed in the bulk substrate beneath the channel region of one or more FETs, with the back gate control region associated with a particular transistor being configured and positioned so that the performance characteristics of that transistor varies in dependence on a bias applied to the back gate control region,
• wherein the size and configuration of the FETs and the size and configuration of the back gate control regions are selected so that the data path cell is specifically adapted for use in the environment of a particular integrated circuit.