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AssigneeSamsung Electronics Co., Ltd.
InventorsJi Hun OH, Donghwan Lee
Estimating the term…
Provided are a delay locked loop (DLL), which is capable of being adopted at a data processing system and include a duty correction circuit, and a duty correction method at the DLL. The duty correction method includes generating first and second delay clock signals having different phase shifts by delaying an external clock signal by as much as first and second set phases in response to a delay control signal, generating first and second first signals respectively synchronized with the first and second delay clock signals, and generating an output clock signal having a set duty ratio by using the first and second pulse signals. According to the foregoing, a more accurate duty correction operation is performed without a half cycle time delay line or a matching delay line.
A delay locked loop (DLL) comprising:
A duty correction method in a delay locked loop (DLL) including a duty correction circuit, comprising:
A data processing system with a delay locked loop (DLL) including a phase detection circuit generating a phase detection signal by comparing a phase of an output clock signal with a phase of an external clock signal and a delay control circuit generating a delay control signal for determining delay time in response to the phase detection signal,
Dependencies are inferred from the claim text.