Stress resistant micro-via structure for flexible circuits
AssigneeGeneral Electric Company
InventorsThomas Bert Gorczyca, Richard Joseph Saia, Paul Alan McConnelee
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AssigneeGeneral Electric Company
InventorsThomas Bert Gorczyca, Richard Joseph Saia, Paul Alan McConnelee
Estimating the term…
A chip package is disclosed that includes an electronic chip having a plurality of die pads formed on a top surface thereof, with a polyimide flex layer positioned thereon by way of an adhesive layer. A plurality of vias is formed through the polyimide flex layer and the adhesive layer corresponding to the die pads. A plurality of metal interconnects are formed on the polyimide flex layer each having a cover pad covering a portion of a top surface of the polyimide flex layer, a sidewall extending down from the cover pad and through the via along a perimeter thereof, and a base connected to the sidewall and forming an electrical connection with a respective die pad. Each of the base and the sidewall is formed to have a thickness that is equal to or greater than a thickness of the adhesive layer.
A chip package comprising:
A method of forming a chip package comprising:
A chip package comprising:
Dependencies are inferred from the claim text.