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US 2011/0215447 A1Published application
Semiconductor chip with seal ring and sacrificial corner pattern
AssigneeRenesas Electronics Corporation
InventorsTakeshi Furusawa, Norio Miura, Kinya Goto, Masazumi Matsuura
Life of this patent
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Abstract
A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
Claims80
A semiconductor device, comprising a low dielectric constant film having a relative dielectric constant less than 3.5, and a seal ring which is a moisture blocking wall forming a closed loop in a plan view, wherein said seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of a chip,
- wherein a passivation film covers said low dielectric constant film and the seal ring, and has a opening penetrating the passivation film, the opening formed in a vicinity of two chip end surfaces in a plan view, said two chip end surfaces forming the corner of the chip.
A semiconductor device, comprising:
- a first insulating layer;
- a second insulating layer including a low dielectric constant film of which a relative dielectric constant is less than 3.5;
- a third insulating layer;
- a semiconductor substrate;
- a seal ring forming a closed loop in a plan view;
- and
- a fourth insulating layer which is made of SiN having an opening penetrating the fourth insulating film and covering said third insulating layer and the seal ring, the opening formed in a vicinity of two chip end surfaces in a plan view, said two chip end surfaces forming a corner of a chip,
- wherein said semiconductor substrate, said first insulating layer, said second insulating layer and said third insulating layer are layered in order of said semiconductor substrate, said first insulating layer, said second insulating layer, said third insulating layer, respectively,
- the seal ring is formed in said first insulating layer, said second insulating layer and said third insulating layer on said semiconductor substrate,
- said seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of the corner of the chip,
- said seal ring protrusion portion protrudes toward a center of said chip between said first insulating layer and said low dielectric constant film, and
- said relative dielectric constant of said low dielectric constant film is less than a relative dielectric constant of said first insulating layer.
9 more elements
A semiconductor device, comprising:
- a semiconductor substrate;
- a first insulating layer formed over said semiconductor substrate;
- a second insulating layer including a low dielectric constant film having a relative dielectric constant less than 3.5, said second insulating layer formed over said first insulating layer;
- a third insulating layer formed over said second insulating layer;
- a seal ring forming a closed loop in a plan view;
- and
- a fourth insulating layer which is made of a SiN having an opening penetrating the fourth insulating film, and covering said third insulating layer and said seal ring, the opening formed in a vicinity of first and second chip end surfaces in a plan view,
- wherein said seal ring is formed in said first insulating layer, said second insulating layer and said third insulating layer on said semiconductor substrate, said seal ring includes a first side formed along the first chip end surface, a second side formed approximately in parallel to the second chip end surface, a third side formed approximately in parallel to said first chip end surface, and a fourth side formed along the second chip end surface in a vicinity of a chip corner, said first chip end surface and said second chip end surface forming said chip corner, said second side formed between said first side and said third side, and said third side formed between said second side and said fourth side,
- one end of said first side is electrically coupled to one end of said second side, another end of said second side is electrically coupled to one end of said third side, and another end of said third side is electrically coupled to one end of said fourth side, and
- said first side, said second side, said third side, and said fourth side are formed between said first insulating layer and said low dielectric constant film, and wherein said relative dielectric constant of said low dielectric constant film is less than a relative dielectric constant of said first insulating layer.
7 more elements
A semiconductor device, comprising:
- a chip;
- and
- a low dielectric constant film having a relative dielectric constant less than 3.5;
- and
- a seal ring which is a moisture blocking wall in closed loop form in a plan view, wherein
- the seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of the chip,
- the seal ring comprising 16 lengths arranged to circumscribe a center point of a surface of said chip, with length 1 connected to length 2, length 2 connected to length 3, length 3 connected to length 4, length 4 connected to length 5, length 5 connected to length 6, length 6 connected to length 7, length 7 connected to length 8, length 8 connected to length 9, length 9 connected to length 10, length 10 connected to length 11, length 11 connected to length 12, length 12 connected to length 13, length 13 connected to length 14, length 14 connected to length 15, length 15 connected to length 16, and length 16 connected to length 1, and
- length 1 is parallel to length 9, length 5 is parallel to length 13, length 3 is parallel to length 11, length 7 is parallel to length 15, length 2 is parallel to length 16, length 4 is parallel to length 6, length 8 is parallel to length 10, and length 12 is parallel to length 14,
- wherein a passivation film covers said low dielectric constant film and said seal ring and has a opening penetrating the passivation film, the opening formed in a vicinity of first and second chip end surfaces in a plan view, said first and said second chip end surfaces forming the corner of the chip.
6 more elements
A semiconductor device, comprising:
- a low dielectric constant film having a relative dielectric constant less than 3.5;
- a seal ring which forming a moisture blocking wall having a closed loop in a plan view;
- and
- an outer seal ring surrounding the seal ring,
- wherein said seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of a chip,
- wherein a passivation film covers said low dielectric constant film and the seal ring, and has an opening penetrating the passivation film, the opening arranged outside of a region surrounded by the seal ring in a plan view.
3 more elements
A semiconductor device, comprising:
- a first insulating layer;
- a second insulating layer including a low dielectric constant film of which a relative dielectric constant is less than 3.5;
- a third insulating layer;
- a semiconductor substrate;
- a seal ring forming a closed loop in a plan view;
- an outer seal ring surrounding the seal ring;
- and
- a fourth insulating layer which is made of SiN having an opening penetrating the fourth insulating film and covering said third insulating layer, the seal ring, and the outer seal ring, the opening arranged outside of a region surrounded by the seal ring in a plan view,
- wherein said semiconductor substrate, said first insulating layer, said second insulating layer and said third insulating layer are layered in order of said semiconductor substrate, said first insulating layer, said second insulating layer, said third insulating layer, respectively,
- each of the seal ring and the outer seal ring is formed in said first insulating layer, said second insulating layer and said third insulating layer on said semiconductor substrate,
- said seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of a chip,
- said seal ring protrusion portion protrudes toward a center of said chip between said first insulating layer and said low dielectric constant film, and
- said relative dielectric constant of said low dielectric constant film is less than a relative dielectric constant of said first insulating layer.
10 more elements
A semiconductor device, comprising:
- a semiconductor substrate;
- a first insulating layer formed over said semiconductor substrate;
- a second insulating layer including a low dielectric constant film having a relative dielectric constant less than 3.5, said second insulating layer formed over said first insulating layer;
- a third insulating layer formed over said second insulating layer;
- a seal ring forming a closed loop in a plan view;
- an outer seal ring surrounding the seal ring;
- and
- a fourth insulating layer which is made of a SiN, has a opening penetrating the fourth insulating film, and covers said third insulating laver, said seal ring, and the outer seal ring, the opening arranged outside of a region surrounded by the seal ring in a plan view,
- wherein said seal ring is formed in said first insulating layer, said second insulating layer and said third insulating layer on said semiconductor substrate,
- said seal ring includes a first side formed along a first chip end surface, a second side formed approximately in parallel to a second chip end surface, a third side formed approximately in parallel to said first chip end surface, and a fourth side formed along the second chip end surface in a vicinity of a chip corner, said first chip end surface and said second chip end surface forming said chip corner, said second side formed between said first side and said third side, and said third side formed between said second side and said fourth side,
- one end of said first side is electrically coupled to one end of said second side, another end of said second side is electrically coupled to one end of said third side, and another end of said third side is electrically coupled to one end of said fourth side, and
- said first side, said second side, said third side, and said fourth side are formed between said first insulating layer and said low dielectric constant film, and said relative dielectric constant of said low dielectric constant film is less than a relative dielectric constant of said first insulating layer.
9 more elements
A semiconductor device, comprising:
- a chip;
- and
- a low dielectric constant film having a relative dielectric constant less than 3.5;
- a seal ring which is a moisture blocking wall forming a closed loop in a plan view;
- and
- an outer seal ring surrounding the seal ring, wherein
- the seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of the chip,
- the seal ring comprising 16 lengths arranged to circumscribe a center point of a surface of said chip, with length 1 connected to length 2, length 2 connected to length 3, length 3 connected to length 4, length 4 connected to length 5, length 5 connected to length 6, length 6 connected to length 7, length 7 connected to length 8, length 8 connected to length 9, length 9 connected to length 10, length 10 connected to length 11, length 11 connected to length 12, length 12 connected to length 13, length 13 connected to length 14, length 14 connected to length 15, length 15 connected to length 16, and length 16 connected to length 1, and
- length 1 is parallel to length 9, length 5 is parallel to length 13, length 3 is parallel to length 11, length 7 is parallel to length 15, length 2 is parallel to length 16, length 4 is parallel to length 6, length 8 is parallel to length 10, and length 12 is parallel to length 14,
- wherein a passivation film covers said low dielectric constant film and said seal ring and has a opening penetrating the passivation film, the opening arranged outside of a region surrounded by the seal ring in a plan view.
7 more elements
Dependencies are inferred from the claim text.