Tunneling field-effect transistor with direct tunneling for enhanced tunneling current
AssigneeSematech, Inc.
InventorsWei-Yip Loh, Brian Coss, Kanghoon Jeon
Life of this patent
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Abstract
Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide.
Claims20
A semiconductor device, comprising:
- a semiconductor layer;
- a first doped region in the semiconductor layer;
- a dielectric layer on the first doped region;
- a second doped region in the semiconductor layer, in which the first doped region and the second doped region are asymmetric;
- and
- a gate stack on the semiconductor layer partially covering the first doped region and partially covering the second doped region.
A semiconductor device, comprising:
- a first semiconductor layer;
- a doped region in the first semiconductor layer;
- a gate stack on the first semiconductor layer including a first sidewall and a second sidewall, the second sidewall partially covering the doped region;
- a second semiconductor layer on the first sidewall;
- a dielectric layer on the second semiconductor layer;
- and
- a third semiconductor layer on the dielectric layer.
A process for manufacturing a semiconductor device, comprising:
- forming a first doped region in a first semiconductor layer;
- depositing a dielectric layer on the first doped region;
- depositing a second semiconductor layer on the dielectric layer;
- etching the second semiconductor layer, the dielectric layer, and the first doped region from a first region;
- depositing a third semiconductor layer on the first semiconductor layer in the first region;
- forming a gate stack on the first semiconductor layer partially covering the third semiconductor layer and the second semiconductor layer;
- forming spacers on the gate stack;
- and
- forming a second doped region in the third semiconductor layer.
A process for manufacturing a semiconductor device, comprising:
- forming a gate stack on a first semiconductor layer;
- forming sidewalls on the gate stack;
- depositing a sacrificial layer on a first side of the gate stack;
- forming a doped region in the first semiconductor layer partially covered by the sacrificial layer;
- depositing a second semiconductor layer on a second side of the gate stack, the second side different from the first side;
- depositing a dielectric layer on the second semiconductor layer;
- depositing a third semiconductor layer on the dielectric layer;
- and
- stripping the sacrificial layer after depositing the third semiconductor layer.
Dependencies are inferred from the claim text.