Pin capacitor of semiconductor device and method for fabricating the same
AssigneeHynix Semiconductor Inc.
InventorJeong-Soo KIM
Life of this patent
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Abstract
A pin capacitor of a semiconductor device includes a first isolation layer formed in a substrate and defining a dummy active area, a plurality of gates formed over the first isolation layer, a spacer formed at both sidewalls of each of the gates, and a plug formed over the dummy active area and in contact with the spacer. The substrate and the plug are coupled to a ground unit, and the gate is coupled to a pad unit. That is, the pin capacitor includes a first capacitor including the gate, the isolation layer, and the substrate and a second capacitor including the gate, the spacer, and the plug, which are coupled in parallel to each other.
Claims20
A pin capacitor of a semiconductor device, comprising:
- a first isolation layer formed in a substrate and defining a dummy active area;
- a plurality of gates formed over the first isolation layer;
- a spacer formed at both sidewalls of each of the gates;
- and
- a plug formed over the dummy active area and in contact with the spacer,
- wherein the substrate and the plug are coupled to a ground unit, and the gate is coupled to a pad unit.
A method for fabricating a pin capacitor of a semiconductor device, comprising:
- forming first and second isolation layers having different widths in a substrate, and defining a plurality of dummy active areas in the substrate;
- forming a plurality of gates over the first isolation layer;
- forming a spacer at both sidewalls of each of the gates, and forming a third isolation layer over the second isolation layer;
- and
- forming a plug over the dummy active areas so as to fill the space between the spacer and the third isolation layer.
A pin capacitor of a semiconductor device, comprising:
- a substrate having an isolation layer and a dummy active area defined by the isolation layer;
- a first capacitor formed between the substrate and a pad of the semiconductor device;
- and
- a second capacitor formed the pad and a plug formed over the dummy active area,
- wherein the first and second capacitors include a gate formed over the isolation area and are coupled in parallel to each other.
Dependencies are inferred from the claim text.