Pin Multiplexing
AssigneeLantiq Deutschland GmbH
InventorsAlvin Lim, Balakrishnan Kangol, Sreekumar Padmanabhan, Sachin Mathur
Life of this patent
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Abstract
A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.
Claims35
A semiconductor device coupled to input/output pins, the semiconductor device comprising:
- a first core to operate a first function;
- a second core to operate a second function;
- an arbiter arranged to receive requests with respect to the first and/or second cores to access the input/output pins and to grant access of the input/output pins with respect to the first and/or second core based on arbitration by the arbiter;
- and
- a register arranged to store a delay value indicative of one of a plurality of delay settings to be applied by the arbiter when granting access of the input/output pins to the second core, wherein the plurality of delay settings are indicative of a different number of clock cycle delays.
A method for multiplexing across a plurality of input/output pins between a first core to operate a first function and a second core to operate a second function, the method comprising:
- sending a request signal to an arbiter for access of the input/output pins with respect to the second core;
- stopping the first core from accessing the input/output pins;
- and
- granting access of the input/output pins to the second core based on a plurality of predetermined delay settings, the predetermined delay settings corresponding to a different number of clock cycle delays.
A method of operating a semiconductor device coupled to input/output pins, the method comprising:
- operating a first function within a first core;
- operating a second function within a second core;
- receiving requests with respect to the first and/or second cores to access the input/output pins;
- granting access of the input/output pins with respect to the first and/or second core based on arbitration by an arbiter;
- and
- storing a delay value in a register, the delay value indicative of one of a plurality of delay settings to be applied when granting access of the input/output pins to the second core, wherein the plurality of delay settings are indicative of a different number of clock cycle delays.
A device for multiplexing across a plurality of input/output pins between a first core to operate a first function and a second core to operate a second function, the device configured to:
- send a request signal to an arbiter for access of the input/output pins with respect to the second core;
- stop the first core from accessing the input/output pins;
- and
- grant access of the input/output pins to the second core based on a plurality of predetermined delay settings, the predetermined delay settings corresponding to a different number of clock cycle delays.
Dependencies are inferred from the claim text.