Heterogeneous transceiver architecture for wide range programmability of programmable logic devices

A serial data receiver comprising:

• a plurality of channels each having a serial bit rate operating range, wherein each of the plurality of channels is operable to receive a serial data signal and operate at a serial bit rate operating range, and wherein a first serial bit rate operating range of a first channel of the plurality of channels exceeds a second serial bit rate operating range of a second channel of the plurality of channels;
• a set of first conductors that distribute a first and a second clock signal to the second channel;
• a second conductor that distributes the second clock signal to the first channel;
• and
• circuitry for allowing the second channel to select the first or the second clock signal for use by the second channel.

A method for configuring a plurality of transceiver channels, the method comprising:

• configuring a first channel of the plurality of transceiver channels to receive a serial data signal, wherein a first serial bit rate operating range of the first channel exceeds a second serial bit rate operating range of a second channel of the plurality of transceiver channels;
• causing a first and a second clock signal to be distributed to the second channel;
• configuring the second clock signal to be coupled to the first channel;
• and
• allowing the second channel to select the first clock signal or the second clock signal for use by the second channel.