US 2011/0211413 A1 · SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

Abstract

A semiconductor memory device includes a plurality of banks, a first bank selection driving control signal generation unit configured to generate a plurality of first bank selection driving control signals corresponding to the plurality of banks in response to an active command signal and an address signal, a second bank selection driving control signal generation unit configured to generate a plurality of second bank selection driving control signals corresponding to the plurality of banks in response to one of a read command signal and a write command signal and in response to the address signal, and an internal voltage driver configured to selectively drive a plurality of internal voltage terminals corresponding to the plurality of banks in response to the plurality of first bank selection driving control signals and the plurality of second bank selection driving control signals.

Claims15

Dependent claims

A semiconductor memory device comprising:

a plurality of banks;
a first bank selection driving control signal generation unit configured to generate a plurality of first bank selection driving control signals corresponding to the plurality of banks in response to an active command signal and an address signal;
a second bank selection driving control signal generation unit configured to generate a plurality of second bank selection driving control signals corresponding to the plurality of banks in response to one of a read command signal and a write command signal and in response to the address signal;
and
an internal voltage driver configured to selectively drive a plurality of internal voltage terminals corresponding to the plurality of banks in response to the plurality of first bank selection driving control signals and the plurality of second bank selection driving control signals.

2 more elements

A method for operating a semiconductor memory device comprising a plurality of banks, the method comprising:

performing a first activation operation of activating a first bank selection driving control signal of a plurality of first bank selection driving control signals in response to an active command signal and an address signal;
performing a second activation operation of activating a second bank selection control signal of a plurality of second bank selection driving control signals in response to one of a read command signal and a write command signal and in response to the address signal;
performing a first driving operation of driving an internal voltage terminal of a bank corresponding to the address signal among the plurality of banks for a length of time in response to the first bank selection driving control signal being activated by the performing of the first activation operation;
and
performing a second driving operation of driving the internal voltage terminal of the bank corresponding to the address signal among the plurality of banks for a length of time in response to the second bank selection driving control signal being activated by the performing of the second activation operation in an interval in which the activated state of the first bank selection driving control signal is maintained.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device and method for operating the same

Life of this patent

Semiconductor memory device and method for operating the same

Life of this patent

Abstract

Claims15