Superconducting circuit for high-speed lookup table

A pipelined processing method, comprising:

• receiving a multibit digital value;
• processing the received multibit digital value with a processing network comprising a pipeline of successive processing stages employing superconducting elements, wherein the digital value is transformed in dependence on pipeline logic and passed to succeeding stages of the pipeline in dependence on a clock cycle;
• and
• presenting an output in dependence on the received digital value, the clock cycle, the pipeline logic and a respective stage of the pipeline with which the output port is associated,
• wherein the pipeline logic implements a code matching network, generating a plurality of output signals corresponding to the multibit digital value, further comprising a plurality of code-matching cells organized into rows and columns, each cell comprising a clocked rapid-single-flux-quantum device, having a column associated with each bit of the multibit digital value, and a row associated a respective output port, wherein the pipeline logic provides a variable time delay between a receipt of the multibit digital value at the input port, and presentation of the output at the output port, of an integral number of clock cycles, a value of the integral number varying in dependence on the multibit digital value,
• and the ouput port is received by a pipelined memory array, which produces an memory output representing a memory contents of at least one memory cell at an address of the pipelined memory array defined by the multibit digital input,
• the memory output having a total time delay between receipt of the multibit digital value and production of the memory output of an integral number of clock cycles that is independent of the multibit digital value.