US 2011/0096882 A1Published application

Method and apparatus for deskewing data transmissions

AssigneeAvalon Microelectronics, Inc.

InventorsWally Haas, Mutema John Pittman

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Abstract

The present invention discloses a method and apparatus for addressing the issue of clock skew in a data signal while making efficient use of space on an integrated chip (IC) by utilising a physical delay line controlled by a state machine in conjunction with pre-requisite chip architecture. The pre-requisite chip architecture samples the incoming data signal in response to a clocking signal input from the physical delay line; the physical delay line responds to commands from the state machine to increment the delay of the physical delay line to produce samples which describe the incoming data signal and delineate its data valid window.

Claims10

Dependent claims

A method for correcting skew in at least one transmitting lane, in a data transmission system, comprising:

a. a data signal comprising plurality of data, wherein said data signal is transmitted across a transmitting lane, whereby said data signal further comprises a plurality of transitions from a first state to a second state;
b. a plurality of data valid windows, wherein each of said plurality of data valid windows comprises a stable portion of said data signal located between a first transition of said data signal and a second transition of said data signal;
c. a timing signal for said data signal comprising a plurality of latching edges, wherein said plurality of latching edges activate at least one circuitry element, whereby said circuitry element obtains a plurality of data samples by sampling said data signal at successive intervals of time;
and
d. a state machine to implement an algorithm to determine a mean length of each of said plurality of data valid windows and further determine a median position of said mean length, wherein said algorithm determines said mean length and said median position through processing said plurality of data samples, wherein each of said plurality of data samples indicates the stability of said data signal at one of a plurality of intervals in one of a plurality of cycles of said data signal, whereby said timing signal is adjusted by said state machine to allow each of said plurality of latching edges to occur in said median position of said mean length of said plurality of data valid windows.

2 more elements

An apparatus for correcting skew in at least one transmitting lane, in a data transmission system, comprising:

a. an input data signal comprising a plurality of data, wherein said input data signal is transmitted across a transmitting lane, whereby said input data signal further comprises a plurality of transitions from a first state to a second state;
b. a plurality of data valid windows, wherein each of said plurality of data valid windows comprises a stable portion of said input data signal located between a first transition of said input data signal and a second transition of said input data signal;
c. an input timing signal for said input data signal comprising a plurality of latching edges;
d. a shift register, wherein said shift register receives said input data signal and samples said input data signal on said plurality of latching edges to obtain a plurality of data samples from said input data signal, whereby said plurality of data samples is output by said shift register as an output data signal, wherein said output data signal is timed by an output timing signal;
and
e. a state machine to request a plurality of iterations of delay from a physical delay element, wherein said physical delay element adds delay to said input timing signal to produce said plurality of iterations of delay in response to said state machine, whereby said state machine processes said plurality of data samples output by said shift register as said output data signal.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/636,947Filed 14 Dec 2009
Priority: CA 268210327 Oct 2009
Published: 28 Apr 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H04L 7/0045
Correction of synchronization errors: correction by a latch cascade
G06F 5/06
Methods or arrangements for data conversion without changing the order or content of the data handled: for changing the speed of data flow, i.e.…
H03K 5/135
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: by the use of time reference…
H03M 9/00
Parallel/series conversion or vice versa

Family

US 8,498,370 B2Related patent
US 2011/0096882 A1This patent

From the US filing history. Foreign family members aren’t listed.

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