Method for layout verification of semiconductor integrated circuit

Abstract

A method for verifying a match between layout patterns of elements provided in a semiconductor integrated circuit, includes a verification condition setting step of setting a verification condition including information about paired elements whose layout patterns should match each other, a layout data input step of inputting layout data including pattern information and arrangement information of the paired elements, and a mismatched pattern parameter calculation layout verifying step of comparing the layout patterns of the paired elements based on the verification condition and the layout data to calculate a distance between the paired elements and at least one mismatched pattern.

Dependencies are inferred from the claim text.