Apparatus and method for local operand bypassing for cryptographic instructions

A method, comprising:

• a hardware processor issuing instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA);
• a hardware functional unit of the processor receiving instructions for execution, wherein the instructions include one or more cryptographic instructions and one or more non-cryptographic instructions;
• the functional unit executing the one or more cryptographic instructions in a cryptographic execution pipeline with a corresponding cryptographic execution latency;
• the functional unit executing the one or more non-cryptographic instructions in a non-cryptographic execution pipeline with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency;
• and
• the functional unit bypassing results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline, such that each instruction within a sequence of dependent cryptographic instructions executes with an execution latency corresponding to the cryptographic execution latency, and wherein the results of the cryptographic execution pipeline are not bypassed to any other functional unit within the processor.

A system, comprising:

• a system memory;
• and
• a processor coupled to the system memory, wherein the processor comprises:
• a hardware instruction fetch unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA);
• and
• a hardware functional unit configured to receive instructions for execution from the instruction fetch unit, wherein the instructions include one or more cryptographic instructions and one or more non-cryptographic instructions, wherein the functional unit comprises:
• a cryptographic execution pipeline configured to execute the one or more cryptographic instructions with a corresponding cryptographic execution latency;
• a non-cryptographic execution pipeline configured to execute the one or more non-cryptographic instructions with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency;
• and
• a local bypass network configured to bypass results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline, such that each instruction within a sequence of dependent cryptographic instructions is executable with an execution latency corresponding to the cryptographic execution latency, and wherein the results of the cryptographic execution pipeline are not bypassed to any other functional unit within the processor.