Multiple-port memory systems and methods

6) A processing system, the processing system comprising:

• at least one processing core;
• a peripheral bus;
• and
• a memory for storing digital data, the memory divided into a first partition of memory segments and a second partition of memory segments, the memory further including
• a first port coupled to the peripheral bus, the first port providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus;
• a second port coupled to the at least one processor, the second port providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core;
• and
• a third port coupled to the at least one processor, the third port providing read access and write access to the entire first partition and the second partition.

16) A method for accessing a multiple port memory device, the method comprising:

• configuring a boundary between memory segments within a memory storage device, the boundary defining a first partition and a second partition within the memory storage device;
• configuring a first port of the memory storage device to provide read access and write access to only the first partition;
• configuring a second port of the memory storage device to provide read-only access only to the second partition;
• and
• configuring a third port of the memory storage device to provide read access and write access to the first partition and the second partition.