Methods relating to capacitive monitoring of layer characteristics during back end-of-the-line processing
AssigneeGlobalfoundries Inc.
InventorsJihong Choi, Yongsik Moon, Roderick Augur, Eden Zielinski
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Abstract
Methods are provided that relate to the capacitive monitoring of characteristic pertaining to layer formed during the back end-of-the-line (BEOL) processing of a semiconductor device. In one embodiment, a method includes the steps of forming a first capacitor array including first and second overlying contacts each formed in a different one of the plurality of BEOL layers, measuring the interlayer capacitance between the first and second overlying contacts, and converting the measured interlayer capacitance to a distance between the first and second overlying contacts.
Claims20
A method for monitoring at least one characteristic pertaining to a plurality of back end-of-the-line (BEOL) layers, the method comprising:
- forming a first capacitor array within the plurality of BEOL layers including first and second overlying contacts each formed in a different one of the plurality of BEOL layers;
- measuring the interlayer capacitance between the first and second overlying contacts;
- and
- converting the measured interlayer capacitance to a distance between the first and second overlying contacts.
A method according to claim 14 wherein the step of forming a first capacitor array comprises forming the first filled trench and the second filled trench each having a first predetermined surface area, and wherein the step of forming a second capacitor array comprises forming the third filled trench and the fourth filled trench each having a second predetermined surface area different than the first predetermined surface area.
A method for manufacturing a plurality of integrated circuits on a semiconductor wafer, comprising:
- fabricating semiconductor devices on the semiconductor wafer;
- forming a plurality of back end-of-the-line (BEOL) layers interconnecting the semiconductor devices;
- and
- monitoring a first characteristic pertaining to the BEOL layers at a plurality of sites on the semiconductor wafer, the step of monitoring comprising:
- forming first and second overlying contacts each in a different one of the plurality of BEOL layers;
- measuring the interlayer capacitance between the first and second overlying contacts;
- and
- converting the measured interlayer capacitance to a distance between the first and second overlying contacts.
A method for manufacturing an integrated circuit, comprising:
- providing a semiconductor wafer;
- fabricating semiconductor devices on the wafer;
- and
- forming a first plurality of back end-of-the-line (BEOL) layers interconnecting the semiconductor devices and in accordance with a design parameter previously determined by the steps comprising:
- (i) forming a second plurality of BEOL layers on test wafer;
- (ii) forming first and second overlying contacts each in a different one of the second plurality of BEOL layers;
- (iii) measuring the interlayer capacitance between the first and second overlying contacts;
- and (iv) converting the measured interlayer capacitance to a distance between the first and second overlying contacts
Dependencies are inferred from the claim text.