Wiring Substrate for a Semiconductor Chip, and Semiconducotor Package Having the Wiring Substrate

Abstract

A wiring substrate for a semiconductor chip includes a substrate, first and second wiring layers and a plurality of first and second bonding pads. The substrate has a first surface and a second surface opposite to the first surface, a window extending from the first surface to the second surface to expose chip pads of a semiconductor chip adherable to the first surface. The first and second wiring layers of a multi-layered structure are sequentially formed on the second surface of the substrate with at least one insulation layer interposed between the first and second wiring layers. A plurality of the first and second bonding pads are respectively connected to the first and second wiring layers, the first and second bonding pads having a concavo-convex arrangement on the second surface of the substrate along a side of the window.

Dependencies are inferred from the claim text.