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US 2011/0079921 A1Published application
Generation of metal holes by via mutation
AssigneesInfineon Technologies AG, International Business Machines Corporation, United Mircroelectronics Corp.
InventorsRobert C. Wong, Ernst H. Demm, Pak Leung, Alexander M. Hirsch
Life of this patent
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Abstract
A semiconductor interconnect architecture provides a reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) without degradation of the product yield or robustness, or increases copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.
Claims8
A semiconductor interconnect architecture, the architecture comprising:
- a first metal layer having provided therein a plurality of holes;
- a second metal layer;
- a plurality of conductive vias interconnecting said first and second metal layers, said plurality of conductive vias comprising a set of redundant vias;
- and
- wherein said plurality of holes are located within said first metal layer at respectively corresponding predetermined positions relative to respective vias of said set of redundant vias.
2 more elements
Dependencies are inferred from the claim text.