Stress buffer to protect device features
AssigneeUnisem Advanced Technologies SDN. BHD.
InventorsSiong Cho Lau, May Nee Lim, Soi Yoke See Thoh, Wai Nam Leong
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Abstract
Disclosed is a stress buffer structure intended to be disposed adjacent a face of a semiconductor substrate. The stress buffer structure includes at least one polymer layer formed on the face of the semiconductor substrate and a plurality of metal plates disposed over the polymer layer, wherein the metal plates is physically and electrically isolated from the bond pads of the semiconductor substrate. The disclosed stress buffer structure provides protection to semiconductor components that are sensitive to stress. Also disclosed are semiconductor packages having the disclosed stress buffer structure and the methods of making the semiconductor packages.
Claims54
A stress buffer structure intended to be disposed adjacent a face of a semiconductor substrate comprising:
- a first polymer layer having at least a first side contacting at least part of a passivation layer formed on said semiconductor substrate, said semiconductor substrate having one or more bond pads on said same face;
- a second polymer layer having a first side that contacts an opposing second side of said first polymer layer;
- and
- a metal plate contacting an opposing second side of said second polymer layer;
- wherein said metal plate has one or more metal layers and is physically and electrically isolated from said bond pads of said semiconductor substrate.
A stress buffer structure intended to be disposed adjacent a face of a semiconductor substrate comprising:
- a first polymer layer having at least a first side contacting at least part of a polymer coating formed on said semiconductor substrate, said semiconductor substrate having one or more bond pads on said same face;
- and
- a metal plate contacting an opposing second side of said first polymer layer;
- wherein said metal plate has one or more metal layers and is physically and electrically isolated from said bond pads of said semiconductor substrate.
A semiconductor package comprising:
- a semiconductor substrate having at least one bond pad and a passivation layer formed on a face of said substrate, said passivation layer having apertures that expose at least a portion of each said bond pad;
- a stress buffer structure disposed adjacent said face of said semiconductor substrate, wherein said stress buffer structure comprises:
- a first polymer layer having at least a first side contacting at least part of said passivation layer;
- a second polymer layer having a first side that contacts an opposing second side of said first polymer layer;
- and
- a metal plate contacting an opposing second side of said second polymer layer;
- wherein said metal plate has one or more metal layers and is physically and electrically isolated from said bond pads of said semiconductor substrate.
A semiconductor package comprising:
- a semiconductor substrate having at least one bond pad and a polymer coating formed on a face of said substrate, said polymer coating having a set of apertures that expose at least a portion of each said bond pad;
- a stress buffer structure disposed on said polymer coating of said semiconductor substrate, wherein said stress buffer structure comprises:
- a first polymer layer having at least a first side contacting at least part of said polymer coating layer;
- and
- a metal plate contacting an opposing second side of said first polymer layer;
- wherein said metal plate has one or more metal layers and is physically and electrically isolated from said bond pads of said semiconductor substrate.
A method for forming a semiconductor package comprising:
- providing a substrate having at least one bond pad and a passivation layer formed thereon, said passivation layer including apertures that expose at least a portion of each said bond pad;
- forming a stress buffer structure over said passivation layer, said stress buffer structure comprising:
- a first polymer layer having at least a first side contacting at least part of said passivation layer;
- a second polymer layer having a first side that contacts an opposing second side of said first polymer layer;
- and
- a metal plate contacting an opposing second side of said second polymer layer;
- wherein said metal plate has one or more metal layers and is physically and electrically isolated from said bond pads of said semiconductor substrate.
A method for forming a semiconductor package comprising:
- providing a substrate having at least one bond pad and a polymer coating formed thereon, said polymer coating including a set of apertures that expose at least a portion of each said bond pad;
- forming a stress buffer structure over said polymer coating, said stress buffer structure comprising:
- a first polymer layer having at least a first side contacting at least part of said polymer coating;
- and
- a metal plate contacting an opposing second side of said first polymer layer;
- wherein said metal plate has one or more metal layers and is physically and electrically isolated from said bond pads of said semiconductor substrate.
Dependencies are inferred from the claim text.