US 2011/0079858 A1 · SEMICONDUCTOR MEMORY DEVICE HAVING A SENSE AMPLIFIER CIRCUIT WITH DECREASED OFFSET

Abstract

A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Claims6

Dependent claims

1-25. (canceled)

A semiconductor device comprising:

a memory array having a plurality of word lines, a plurality of data lines, and a plurality of memory cells arranged at respective intersections of the plurality of word lines and the plurality of data lines, and
a respective sense amplifier circuit connected to each of the plurality of data line pairs of the plurality of the data lines,
wherein the sense amplifier circuit has a first MISFET pair, a second MISFET pair, and a third MISFET pair,
the first and second MISFET pairs are of a first conduction type and the third MISFET pair is of a second conduction type which is opposite to the first conduction type,
a gate of one of the first MISFET pair and one of the data line pairs, which is included in the plurality of data lines and is provided corresponding to a drain of the other of the first MISFET pair, are connected with each other,
a gate of one of the second MISFET pair and a drain of the other of second MISFET pair are connected with each other,
a gate of one of the third MISFET pair and a drain of the other of the third MISFET pair are connected with each other,
the first MISFET pair includes a first transistor having the first conduction type and a second transistor having the first conduction type,
the drain of the first transistor is connected with the source of a fourth MISFET having the first conduction type,
the drain of the second transistor is connected with the source of a fifth MISFET having the first conduction type,
drains of the fourth and fifth MISFETs are connected to the data line pair, respectively,
the fourth and fifth MISFETs are activated to drive the first MISFET pair preceding to the second MISFET pair and the third MISFET pair, and
the fourth and fifth MISFETs are inactivated before a corresponding one of the plurality of word lines is inactivated.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/967,728Filed 14 Dec 2010

Priority

JP 2007-0014559 Jan 2007

Published

7 Apr 2011

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

G11C 11/4091
Read-write [R-W] circuits: sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or…
H10B 12/50
Dynamic random access memory [DRAM] devices: peripheral circuit region structures
G11C
Static stores
H10B
Electronic memory devices

Semiconductor memory device having a sense amplifier circuit with decreased offset

Life of this patent

Semiconductor memory device having a sense amplifier circuit with decreased offset

Life of this patent

Abstract

Claims6