Dram cell with double-gate fin-fet, dram cell array and fabrication method thereof

A method for fabricating a memory cell array, comprising:

• providing a semiconductor substrate having thereon at least one pad layer;
• forming a plurality of first and second line-shaped trenches in parallel to one another in the semiconductor substrate;
• filling the first and second line-shaped trenches with first trench fill dielectric;
• forming a plurality of third line-shaped trenches into the semiconductor substrate, wherein the third line-shaped trenches intersect with the first and second line-shaped trenches, thereby forming a plurality of top silicon islands;
• forming a spacer on sidewall of the top silicon islands;
• etching, in a self-aligned manner, deep trenches into the semiconductor substrate through the third line-shaped trenches;
• etching a lower portion of each of the deep trenches to form a fin channel structure under each of the top silicon islands and a sidewall recess under the spacer;
• forming a gate dielectric layer on interior surface of the lower portion of each of the deep trenches;
• forming a sidewall buried word line inlaid in the sidewall recess;
• filling the deep trenches with second trench fill dielectric;
• stripping the pad layer to form a plurality of recessed implant windows;
• implanting dopants into the top silicon islands through the recessed implant windows, to thereby form source/drain regions;
• and
• forming bit lines and storage capacitors electrically connecting to corresponding said source/drain regions.