Frequency Divider and Method for Frequency Division

A frequency divider, comprising:

• a first and a second triggered delay element, each having a data input, a trigger control input and a data output, the delay elements configured to forward a state of an input signal at their respective data input to their respective data output, wherein it depends on a control signal at the respective trigger control input of the delay element whether the state is forwarded either for a rising clock edge of an input clock signal or for a falling clock edge of the input clock signal;
• and
• a clock output;
• wherein the data input and the trigger control input of the first delay element are coupled to the clock output, wherein one input of said data input and said trigger control input is coupled to the clock output by first inverting means;
• wherein the data input and the trigger control input of the second delay element are coupled to the data output of the first delay element, wherein one input of said data input and said trigger control input is coupled to said data output by second inverting means in a complementary fashion with respect to the first delay element;
• and
• wherein the clock output is coupled to the data output of the second delay element.

A method for frequency division, comprising:

• providing an input clock signal;
• deriving a first input state of a plurality of at least two input states from a last data signal of a plurality of at least two data signals;
• deriving a first selection signal of a plurality of at least two selection signals from the last data signal, the first selection signal pertaining to the first input state;
• deriving a first data signal of the plurality of at least two data signals by forwarding the first input state, wherein it depends on the first selection signal whether the first input state is forwarded either at a rising clock edge of the input clock signal or at a falling clock edge of the input clock signal;
• deriving a further input state of the plurality of at least two input states from a respective preceding data signal of the plurality of at least two data signals;
• deriving a further selection signal of the plurality of at least two selection signals from the respective preceding data signal, the further selection signal pertaining to the further input state;
• deriving a further data signal of the plurality of at least two data signals by forwarding the further input state, wherein it depends on the further selection signal whether the further input state is forwarded either at a rising clock edge of the input clock signal or at a falling clock edge of the input clock signal;
• and
• deriving an output clock signal from one data signal of the plurality of at least two data signals;
• wherein one of the plurality of at least two selection signals is derived by inverting the corresponding data signal and wherein the input states not pertaining to said one selection signal are derived by inverting the corresponding data signals.