Semiconductor memory device and a method of manufacturing the same
AssigneeRenesas Electronics Corporation
InventorsMasahiro MONIWA, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
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Abstract
A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
Claims8
A method of manufacturing a semiconductor device including MISFETs, comprising steps of:
- (a) forming a first film over a conductive film formed over a main surface of a semiconductor substrate;
- (b) patterning the first film to form first patterns each having a shape extending in a first direction;
- (c) patterning the first patterns in a second direction perpendicular to the first direction to form second patterns each separated in the first direction;
- and
- (d) patterning the conductive film by using the second patterns to form a gate electrode of a first MISFET and a gate electrode of a second MISFET,
- wherein the gate electrode of the first MISFET and the gate electrode of the second MISFET are arranged, in the first direction, adjacent to each other.
A method of manufacturing a semiconductor device including MISFETs, comprising steps of:
- (a) forming a first film over a conductive film formed over a main surface of a semiconductor substrate;
- (b) patterning the first film to form first patterns each having a shape extending in a first direction;
- (c) patterning the first patterns in a second direction perpendicular to the first direction to form second patterns each separated in the first direction;
- and
- (d) patterning the conductive film by using the second patterns to form a plurality of gate electrodes of MISFETs such that the MISFETs are arranged, in the first direction, adjacent to each other.
Dependencies are inferred from the claim text.