Method for manufacturing semiconductor device
AssigneeElpida Memory, Inc.
InventorShigeru SHIRATAKE
Life of this patent
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Abstract
A method for manufacturing a semiconductor device whereby the process is simplified and high performance can be obtained in both a trench-gate transistor and a planar transistor that has a thin gate insulating film when the two transistors are formed on the same semiconductor substrate. In a state in which the gate insulating film (11s) in a peripheral circuit region PE is covered by a protective film (12), a gate trench (18) is formed in a memory cell region M, after which a gate insulating film (19) that is thicker than the gate insulating film (11s) is formed on an inner wall of the gate trench (18) in a state in which the gate insulating film (11s) of the peripheral circuit region PE is still covered by the protective film (12).
Claims13
1-12. (canceled)
A method of manufacturing a semiconductor device including a first region in which a trench transistor is formed and a second region in which a planar transistor is formed, the method comprising:
- forming an insulating film over the first and second regions, the first insulating film thereby including a first portion over the first region and a second portion over the second region;
- forming a protective film over the insulating film, the protective film thereby including a first portion over the first portion of the insulating film and a second portion over the second portion of the insulating film;
- forming a trench in the first region by selectively removing the first portions of the insulating film and the protective film;
- and
- forming a gate insulating film of the trench transistor over a surface of the trench, the gate insulating film being larger in thickness than the insulating film.
A method of manufacturing a semiconductor device including a first region in which a trench transistor is formed and a second region in which a planar transistor is formed, the method comprising:
- forming an insulating film over the first and second regions, the insulating film thereby including a first portion over the first region and a second portion over the second region;
- forming a protective film over the insulating film, the protective film thereby including a first portion over the first portion of the insulating film and a second portion over the second portion of the insulating film;
- forming a trench in the first region by selectively removing first portions of the insulating film and the protective film;
- forming a gate insulating film of the trench transistor over a surface of the trench, the gate insulating film being different in thickness from the insulating film;
- and
- selectively removing the second portions of the insulating film and the protective film to leave a portion of the insulating film that serves as a gate insulating film of the planar transistor.
A method comprising:
- defining into a semiconductor layer a first region in which a first transistor is to be formed and a second region in which a second transistor is to be formed;
- forming an insulating layer on the first and second regions, the insulating layer including a first portion on the first region and a second portion on the second region;
- removing a part of the first portion of the insulating layer from the first region to define a gate formation portion in the first region, the removing the part of the first portion of the insulating layer being carried out while leaving the second portion of the insulating layer on the second region;
- forming a first gate insulating film of the first transistor on the gate formation portion, the first gate insulating film being different in thickness from the insulating layer;
- and
- selectively removing the insulating layer from the second region to leave a part of the insulating layer on the second region, the part of the insulating layer serving as a second gate insulating film of the second transistor.
Dependencies are inferred from the claim text.