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US 2011/0032752 A1Published application
Multi-Level Memory Device Using Resistance Material
AssigneeSamsung Electronics Co., Ltd.
InventorsIk-Soo Kim, Do-Hyung KIM, Sung-Lae CHO, Hyeong-Geun AN, Dong-Hyun IM, Eun-Hee CHO
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Abstract
A multi-level memory device includes an insulating layer having an opening therein, and a multi-level cell (MLC) formed in the opening that has a resistance level varies based on the data stored therein. The MLC is configured to have a resistance level that varies as write pulses having the same pulse height and different pulse widths are applied to the MLC.
Claims21
A multi-level memory device comprising:
- an insulating layer including an opening;
- a multi-level cell (MLC) formed in the opening;
- and
- a write circuit that is configured to store one of a plurality of data values in the MLC by applying a respective one of a plurality of write pulses to the MLC, wherein each of the plurality of write pulses has the same pulse height and a different pulse width,
- wherein the MLC is configured to have a resistance level that varies with the width of the write pulse that is applied thereto so that the write pulses having different widths may be used to store different data values in the MLC.
2 more elements
A multi-level memory device comprising:
- a multi-level cell (MLC);
- and
- a write circuit that is configured to store one of a plurality of data values in the MLC by applying a respective one of a plurality of write pulses to the MLC, wherein each of the plurality of write pulses has the same pulse height and a different pulse width,
- wherein the MLC is configured to have a variable resistance level that decreases as the pulse widths of the write pulses increase.
1 more element
A multi-level memory device comprising:
- a multi-level cell (MLC) having a confined structure and a resistance level that varies based on the data stored therein, the MLC including only one kind of phase change material (PCM);
- and
- a write circuit that is configured to store one of a plurality of data values in the MLC by applying a respective one of a plurality of write pulses to the MLC, wherein each of the plurality of write pulses has a different pulse width,
- wherein the MLC is configured so that a ratio of a crystalline area to an amorphous area in the PCM is greater for ones of the plurality of write pulses that have increased pulse widths.
1 more element
21-25. (canceled)
Dependencies are inferred from the claim text.