US 2011/0031954 A1 · Driving power-supply circuit

Abstract

The object of the present invention is reducing power consumption of a driving power supply circuit. In the case where the driving voltage Vi is higher than the reference voltage ViH, The signal S3P, S3N of the differential amplifier 30P, 30N become level “L” concurrently, and the signal S4P, S4N of the output circuit 40P, 40N become level “H”. Subsequently, the NMOS 62 becomes on-state and decreases the driving voltage Vi of the node N6. At the above stage, the control signal CP becomes level “L”, then the operation of the constant current circuit 20P is halted.

Claims7

Dependent claims

(canceled)

A driving power supply circuit for controlling a driving voltage to have a voltage between a lower reference voltage and an upper reference voltage and for outputting said driving voltage from an output node comprising;

a p-channel MOS transistor connected between a power supply conductor and said output node and being configured to be on when a first signal has a first logic level and to be off when said first signal has a second logic level;
a n-channel MOS transistor connected between said output node and a ground conductor and being configured to be off when a second signal has the first logic level and to be on when said second signal has the second logic level;
a logic circuit configured to output a first control signal when said first signal and said second signal have the first logic level, to output a second control signal when said first signal and said second signal have the second logic level, and to output a third control signal when said first signal has the second logic level and said second signal has the first logic level;
a first comparing circuit configured to compare said driving voltage to said lower reference voltage in a high-speed-operation mode in response to said first control signal, to compare said driving voltage to said lower reference voltage in a low-power-consumption mode in response to said third control signal, to set said first signal to the second logic level and output said first signal to said p-channel MOS transistor when said driving voltage is higher than said lower reference voltage, and to set said first signal to the first logic level and output said first signal to said p-channel MOS transistor when said driving voltage is lower than said lower reference voltage;
and
a second comparing circuit configured to compare said driving voltage to said upper reference voltage in a high-speed-operation mode in response to said second control signal, to compare said driving voltage to said upper reference voltage in a low-power-consumption mode in response to said third control signal, to set said second signal to the second logic level and output said second signal to said n-channel transistor when said driving voltage is higher than said upper reference voltage, and to set said second signal to the first logic level and output said second signal to said n-channel transistor when said driving voltage is lower than said reference voltage.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/923,114Filed 2 Sep 2010

Priority

JP 2005-21977029 Jul 2005

Published

10 Feb 2011

Term ends

Not estimatedThe source records don’t support an estimate.

Classification3 codes

G09G 3/3696
Control of matrices with row and column drivers: generation of voltages supplied to electrode drivers
G09G 2330/021
Details of power systems and of start or stop of display operation: power management, e.g. power saving
G09G
Arrangements or circuits for control of indicating devices using static means to

Abstract

Claims7

Dependent claims

(canceled)

a p-channel MOS transistor connected between a power supply conductor and said output node and being configured to be on when a first signal has a first logic level and to be off when said first signal has a second logic level;
a n-channel MOS transistor connected between said output node and a ground conductor and being configured to be off when a second signal has the first logic level and to be on when said second signal has the second logic level;
a logic circuit configured to output a first control signal when said first signal and said second signal have the first logic level, to output a second control signal when said first signal and said second signal have the second logic level, and to output a third control signal when said first signal has the second logic level and said second signal has the first logic level;
a first comparing circuit configured to compare said driving voltage to said lower reference voltage in a high-speed-operation mode in response to said first control signal, to compare said driving voltage to said lower reference voltage in a low-power-consumption mode in response to said third control signal, to set said first signal to the second logic level and output said first signal to said p-channel MOS transistor when said driving voltage is higher than said lower reference voltage, and to set said first signal to the first logic level and output said first signal to said p-channel MOS transistor when said driving voltage is lower than said lower reference voltage;
and
a second comparing circuit configured to compare said driving voltage to said upper reference voltage in a high-speed-operation mode in response to said second control signal, to compare said driving voltage to said upper reference voltage in a low-power-consumption mode in response to said third control signal, to set said second signal to the second logic level and output said second signal to said n-channel transistor when said driving voltage is higher than said upper reference voltage, and to set said second signal to the first logic level and output said second signal to said n-channel transistor when said driving voltage is lower than said reference voltage.

3 more elements

Dependencies are inferred from the claim text.

Driving power-supply circuit

Life of this patent

Abstract

Claims7

Driving power-supply circuit

Life of this patent

Abstract

Claims7