Embedded laminated device

A laminate insert package comprising:

• at least one semiconductor chip, each semiconductor chip defining a first main face and a second main face opposite to the first main face;
• a first metal layer coupled to the first main face of the at least one semiconductor chip;
• a second metal layer coupled to the second main face of the at least one semiconductor chip;
• and
• a first insulating layer adjacent to the at least one semiconductor chip and between the first metal layer and the second metal layer;
• wherein the first insulating layer is a printed resin layer.

A method of manufacturing an electronic device comprising:

• providing a laminate insert package comprising at least one semiconductor chip, a first metal layer coupled to a first main face of the at least one semiconductor chip and a second metal layer coupled to a second main face of the at least one semiconductor chip opposite to the first main face;
• applying the laminate insert package over a third metal layer;
• applying a fourth metal layer over the laminate insert package;
• producing at least one first through-connection extending from the third metal layer to the fourth metal layer, the at least one first through-connection being electrically connected with the first metal layer and electrically disconnected from the second metal layer;
• and
• producing at least one second through-connection extending from the third metal layer to the fourth metal layer, the at least one second through-connection being electrically connected with the second metal layer and electrically disconnected from the first metal layer.

A method of producing a laminate insert package comprising

• providing a first metal layer;
• printing a first dielectric layer on the first metal layer;
• providing a second metal layer;
• printing a second dielectric layer on the second metal layer;
• printing a dielectric spacer layer on the first dielectric layer;
• attaching at least one semiconductor chip to either the first or the second metal layer;
• bringing a first layer assembly comprising the first metal layer, the first dielectric layer, the dielectric spacer layer and a second layer assembly comprising the second metal layer and the second dielectric layer together;
• and
• laminating the first and second layer assemblies to form a laminate insert package, whereby the at least one semiconductor chip is embedded within the laminate insert package.