Read-only memory and method of manufacture thereof

A mask-defined read-only memory array formed on a substrate, the mask-defined read-only memory array comprising:

• a first ROM bit of a first polarity, the first ROM bit comprising:
• a first block layer formed over a first region of the substrate;
• a first metal-oxide-silicon (MOS) transistor comprising:
• a first source/drain diffusion region formed outside the first region of the substrate on a first side of the first block layer;
• a second source/drain diffusion region formed in the first region of the substrate;
• and
• a first gate layer electrically connected to a first word line for inducing a channel between the first source/drain diffusion region and the second source drain diffusion region;
• a first contact electrically connected to the first source/drain diffusion region for receiving a first select signal;
• a first diffusion region formed in the first region of the substrate on a second side of the first block layer different from the first side of the first block layer;
• and
• a second contact electrically connected to the first diffusion region for receiving a second select signal;
• and
• a second ROM bit of a second polarity opposite the first polarity, the second ROM bit comprising:
• a second block layer formed over a second region of the substrate different from the first region;
• a second metal-oxide-silicon (MOS) transistor comprising:
• a third source/drain diffusion region;
• a fourth source/drain diffusion region formed in the second region;
• a second gate layer formed between the third source/drain diffusion region and the fourth source/drain diffusion region, the second gate layer electrically connected to a second word line for inducing a channel between the third source/drain diffusion region and the fourth source drain diffusion region;
• and
• an extended gate layer formed from the second gate layer to the second block layer;
• a third contact electrically connected to the third source/drain diffusion region for receiving a third select signal;
• and
• a fourth contact electrically connected to the fourth source/drain diffusion region for receiving a fourth select signal.

A mask-defined read-only memory array formed on a substrate, the mask-defined read-only memory array comprising:

• a first ROM bit of a first polarity, the first ROM bit comprising:
• a first floating layer;
• a first metal-oxide-silicon (MOS) transistor comprising:
• a first source/drain diffusion region;
• a second source/drain diffusion region;
• a first inter-polysilicon dielectric layer formed on the first floating layer;
• and
• a first gate layer formed on the first inter-polysilicon dielectric layer, the first gate layer electrically connected to a first word line;
• a first contact electrically connected to the first source/drain diffusion region for receiving a first select signal;
• and
• a second contact electrically connected to the second source/drain diffusion region for receiving a second select signal;
• and
• a second ROM bit of a second polarity opposite the first polarity, the second ROM bit comprising:
• a second floating layer;
• a second metal-oxide-silicon (MOS) transistor comprising:
• a third source/drain diffusion region;
• a fourth source/drain diffusion region;
• and
• a second gate layer formed on the second floating layer, the second gate layer electrically connected to a second word line for inducing a channel between the third source/drain diffusion region and the fourth source drain diffusion region;
• a third contact electrically connected to the third source/drain diffusion region for receiving a third select signal;
• and
• a fourth contact electrically connected to the fourth source/drain diffusion region for receiving a fourth select signal.

A method of transforming a one-time programming (OTP) memory into coded non-volatile memory on a substrate, the method comprising:

• forming a first polysilicon gate over a first region of the substrate;
• forming a second polysilicon gate over a second region of the substrate different from the first region;
• forming a block layer parallel to the first polysilicon gate over the first region of the substrate, wherein the block layer and the first polysilicon gate are not electrically connected;
• forming a first diffusion region on a first side of the first polysilicon gate, a second diffusion region between the first polysilicon gate and the block layer, a third diffusion region on a side of the block layer opposite the second diffusion region, a fourth diffusion region on a first side of the second polysilicon gate, and a fifth diffusion region on a side of the second polysilicon gate opposite the fourth diffusion region;
• and
• forming a first contact on the first diffusion region, a second contact on the third diffusion region, a third contact on the fourth diffusion region, and a fourth contact on the fifth diffusion region.

A method of transforming a one-time programming (OTP) memory into coded non-volatile memory on a substrate, the method comprising:

• forming a first polysilicon gate over a first region of the substrate;
• forming a floating polysilicon layer parallel to the first polysilicon gate over the first region of the substrate, wherein the floating polysilicon layer and the first polysilicon gate are not electrically connected;
• forming a second polysilicon gate over a second region of the substrate different from the first region;
• forming an extended polysilicon gate layer adjacent to the second polysilicon gate, wherein the extended polysilicon gate layer and the second polysilicon gate are electrically connected;
• forming a first diffusion region on a first side of the first polysilicon gate, a second diffusion region between the first polysilicon gate and the floating polysilicon layer, a third diffusion region on a side of the floating polysilicon layer opposite the second diffusion region, a fourth diffusion region on a first side of the second polysilicon gate, and a fifth diffusion region on a side of the extended polysilicon gate layer opposite the fourth diffusion region;
• and
• forming a first contact on the first diffusion region, a second contact on the third diffusion region, a third contact on the fourth diffusion region, and a fourth contact on the fifth diffusion region.

A method of transforming a one-time programming (OTP) memory into coded non-volatile memory on a substrate, the method comprising:

• forming a first floating polysilicon layer over a first region of the substrate;
• forming an inter-polysilicon dielectric layer on the first floating polysilicon layer;
• forming a first gate layer on the inter-polysilicon dielectric layer;
• forming a second floating polysilicon layer over a second region of the substrate different from the first region while forming the first floating polysilicon layer;
• forming a second gate layer on the second floating polysilicon layer while forming the first gate layer;
• forming a first diffusion region on a first side of the first gate layer, a second diffusion on a side of the first gate layer opposite the first diffusion region, a third diffusion region on a first side of the second gate layer, and a fourth diffusion region on a side of the second gate layer opposite the third diffusion region;
• and
• forming a first contact on the first diffusion region, a second contact on the second diffusion region, a third contact on the third diffusion region, and a fourth contact on the fourth diffusion region.