Back to results
US 2011/0031538 A1Published application
Cmos structure with multiple spacers
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsBor Chiuan HSIEH, Han-Ping CHUNG, Chih-Hsin KO, Bor-Wen CHAN, Hun-Jan TAO
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.
Claims21
A semiconductor device comprising:
- a substrate having shallow trench isolation regions and source/drain regions therein;
- a gate stack overlying the substrate between the source/drain regions;
- a first spacer with a first dielectric constant overlying a sidewall of the gate stack, wherein the first spacer has an exterior sidewall;
- and
- a second spacer with a second dielectric constant overlying the exterior sidewall of the first spacer, wherein the first dielectric constant is less than the second dielectric constant.
2 more elements
A MOS device comprising:
- a semiconductor substrate having shallow trench isolation (STI) regions therein;
- a gate stack overlying the semiconductor substrate between the STI regions;
- lightly doped source/drain (LDD) regions in the semiconductor substrate, wherein the LDD regions are substantially aligned respectively with the edges of the gate stack;
- a boron-doped gate spacer overlying a sidewall of the gate stack;
- and
- a protection spacer located overlying an exterior sidewall of the boron-doped spacer, wherein the protection spacer compass the boron-doped gate spacer.
3 more elements
A MOS device comprising:
- a semiconductor substrate having shallow trench isolation (STI) regions therein;
- a gate stack located on the semiconductor substrate between the STI regions;
- lightly doped source/drain (LDD) regions in the semiconductor substrate, wherein the LDD regions are substantially aligned respectively with the edges of the gate stack;
- oxide liners located on sidewalls of the gate stack;
- boron-doped dielectric spacers located on exterior sidewalls of the oxide liners;
- non-doped dielectric spacers located on exterior sidewalls of the boron-doped dielectric spacers, wherein the non-doped dielectric spacers compass the boron-doped dielectric spacers respectively;
- and
- source/drain regions in the semiconductor substrate and substantially aligned respectively with the edges of the non-doped dielectric spacers.
5 more elements
Dependencies are inferred from the claim text.