Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit
AssigneePanasonic Corporation
InventorsNana Okamoto, Masaki Tamaru, Hidetoshi Nishimura
Life of this patent
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Abstract
In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.
Claims26
A layout structure of a standard cell having a first transistor, a second transistor, and a third transistor which are connected to each other in series, the first transistor and the second transistor sharing a first impurity diffusion region, and the second transistor and the third transistor sharing a second impurity diffusion region, wherein
- at least one dummy via contact is provided on any one of the first impurity diffusion region and the second impurity diffusion region, and
- the dummy via contact is connected to the impurity diffusion region.
A layout structure of a standard cell having a first transistor and a second transistor which are connected to each other in series, the first transistor and the second transistor sharing an impurity diffusion region, wherein
- at least one dummy via contact is provided on the impurity diffusion region, and
- the dummy via contact is connected to the impurity diffusion region.
A layout structure of a standard cell having a first transistor, a second transistor, and a third transistor which are connected to each other in series, the first transistor and the second transistor sharing a first impurity diffusion region, and the second transistor and the third transistor sharing a second impurity diffusion region, wherein
- at least one dummy via contact is provided on at least one of the first impurity diffusion region and the second impurity diffusion region, and
- the dummy via contact is connected to the impurity diffusion region.
A layout structure of a standard cell having an off transistor, wherein
- the off transistor has impurity diffusion regions, and
- a dummy via contact is provided on at least one of the impurity diffusion regions.
A layout structure of a standard cell having dummy impurity diffusion regions, wherein
- a dummy via contact is provided on at least one of the dummy impurity diffusion regions.
A layout structure of a standard cell having transistors, wherein
- a dummy via contact is provided on a gate of at least one of the transistors.
A layout structure of a standard cell having dummy gates, wherein
- a dummy via contact is provided on at least one of the dummy gates.
Dependencies are inferred from the claim text.