Method and design system for semiconductor integrated circuit
AssigneeNEC Electronics Corporation
InventorDaishin Itagaki
Life of this patent
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AssigneeNEC Electronics Corporation
InventorDaishin Itagaki
Estimating the term…
A layout region in which a wiring pattern and a special pattern are placed is divided into division regions. The minimum pitch for the special pattern is larger than the minimum pitch for the wiring pattern. With respect to each division region, the special pattern included in a predetermined region surrounding the each division region is extracted as a peripheral pattern, and a dummy pattern placement region included in the each division region is determined. The dummy pattern placement region is apart from at least one of boundaries between adjacent division regions. A dummy pattern is added in the dummy pattern placement region with avoiding a design rule error with the peripheral pattern existing around the each division region. Then, the plurality of division regions to which the dummy pattern is added are coupled with each other.
A method of designing a semiconductor integrated circuit comprising:
A design system for a semiconductor integrated circuit, comprising:
Dependencies are inferred from the claim text.