Correlating Instruction Sequences with CPU Performance Events to Improve Software Performance
AssigneeAdvanced Micro Devices, Inc.
InventorGary R. Frost
Life of this patent
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Abstract
A system and method are disclosed for correlating instruction sequences. A plurality of instructions is processed to parse a first sequence of instructions comprising a first area of interest. A first instruction sequence pattern is then generated from the first sequence of instructions. Pattern matching operations are performed with the first instruction sequence pattern. A second sequence of instructions are parsed, comprising a second instruction sequence pattern and a second address of interest that is a substantially equivalent match to the first instruction sequence pattern.
Claims20
A system for correlating instruction sequences, comprising:
- processing logic operable to process a plurality of instructions to:
- parse a first sequence of instructions comprising a first address of interest;
- generate a first instruction sequence pattern from said first sequence of instructions;
- and
- perform pattern matching operations with said first instruction sequence pattern to parse a second sequence of instructions comprising a second instruction sequence pattern and a second address of interest;
- an interface operable to:
- receive input data associated with said first address of interest;
- and
- provide output data associated with said second address of interest;
- wherein said second instruction sequence pattern is an equivalent of said first instruction sequence pattern.
A method for correlating instruction sequences, comprising:
- using processing logic to process a plurality of instructions to:
- parse a first sequence of instructions comprising a first address of interest;
- generate a first instruction sequence pattern from said first sequence of instructions;
- and
- perform pattern matching operations with said first instruction sequence pattern to parse a second sequence of instructions comprising a second instruction sequence pattern and a second address of interest;
- using an interface to:
- receive input data associated with said first address of interest;
- and
- provide output data associated with said second address of interest;
- wherein said second instruction sequence pattern is an equivalent of said first instruction sequence pattern.
Dependencies are inferred from the claim text.