US 2010/0306513 A1 · Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline

Abstract

A processor core and method for managing program counter redirection in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.

Claims13

Dependent claims

A non-transitory computer-readable storage medium having stored thereon computer-readable program code to generate a processor core having an out-of-order pipeline, the processor core comprising:

an instruction identification generator that generates instruction identification tags used to identify a program order of instructions;
and
a mispredict instruction identification checker that compares a first instruction identification tag associated with a first control transfer instruction to a second instruction identification tag stored in a register of the mispredict instruction identification checker, the second identification tag being associated with a second control transfer instruction,
wherein if the comparison of the first instruction identification tag and the second instruction identification tag indicates that the first control transfer instruction executed out of program order relative to the second control transfer instruction, the mispredict instruction identification checker generates a signal that enables instruction fetching to be redirected in accordance with a program counter value associated with the first control transfer instruction.

1 more element

A non-transitory computer-readable storage medium having stored thereon computer-readable program code to generate a processor core having an out-of-order pipeline, the processor core comprising:

first computer readable program code for providing an instruction identification generator that generates instruction identification tags used to identify a program order of instructions;
and
second computer readable program code for providing a mispredict instruction identification checker that compares a first instruction identification tag associated with a first control transfer instruction to a second instruction identification tag stored in a register of the mispredict instruction identification checker, the second identification tag being associated with a second control transfer instruction,
wherein if the comparison of the first instruction identification tag and the second instruction identification tag indicates that the first control transfer instruction executed out of program order relative to the second control transfer instruction, the mispredict instruction identification checker generates a signal that enables instruction fetching to be redirected in accordance with a program counter value associated with the first control transfer instruction.

1 more element

Dependencies are inferred from the claim text.

Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline

Life of this patent

Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline

Life of this patent

Abstract

Claims13