Single cycle data movement between general purpose and floating-point registers

A method of fabricating a core adapted for providing functionality to move data between register files in a processor that includes an integer execution unit and a floating-point execution unit, the method comprising:

• providing an integer unit that includes an integer execution unit that is operative to execute one or more types of instructions with single cycle latency;
• positioning an integer register file (IRF) proximate to the integer execution unit inside the integer unit;
• positioning a floating-point register file (FRF) proximate to the integer execution unit inside the integer unit;
• and
• moving data between a register of the IRF and a register of the FRF with single cycle latency using the integer execution unit.

A computer implemented method for moving data between register files of a processor, the processor comprising an integer unit that includes an integer execution unit that is operative to execute one or more types of instructions with single cycle latency, an integer register file (IRF) coupled to the integer execution unit, and a floating-point register file (FRF) coupled to the integer execution unit;

• a floating-point execution unit that is operative to execute one or more types of instructions with multiple cycle latency;
• and a data bus that couples the floating-point execution unit to the integer unit, the method comprising:
• moving the data of a source register to a destination register by executing program code on the processor, the source register being a register in one of the IRF and the FRF, and the destination register being a register in another one of the IRF and the FRF;
• and
• performing the moving of the data using the integer execution unit of the integer unit with single cycle latency.