Out-of-order execution microprocessor with reduced store collision load replay reduction

A method for reducing the likelihood of having to replay a load instruction in an out-of-order execution microprocessor due to a store collision, the microprocessor having a register alias table (RAT) configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order, the method comprising:

• allocating an entry in a queue of entries, in response to the RAT encountering a store instruction;
• populating information in the allocated entry that identifies sources of the store instruction used to compute its store address;
• populating the allocated entry to hold a dependency that identifies an instruction upon which the store instruction depends for its data;
• determining, in response to the RAT encountering a load instruction, whether sources of the load instruction used to compute its load address match the sources of the store instruction in an entry of the queue;
• and
• causing the load instruction to share the dependency of the matching store instruction if the load instruction sources match the store instruction sources in an entry of the queue.

A computer program product for use with a computing device, the computer program product comprising:

• a computer usable storage medium, having computer readable program code embodied in said medium, for specifying a an out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision, the computer readable program code comprising:
• first program code for specifying a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a dependency that identifies an instruction upon which the store instruction depends for its data;
• and
• second program code for specifying a register alias table (RAT), coupled to the queue of entries, the RAT configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order, wherein in response to encountering a load instruction the RAT determines whether sources of the load instruction used to compute its load address match the sources of the store instruction in an entry of the queue, and if so, causes the load instruction to share the dependency of the matching store instruction.