Apparatus and method for address generation for array processor and array processor
AssigneeNEC Corporation
InventorTomoyoshi Kobori
Life of this patent
Estimating the term…
Abstract
In address generation processors, the start and the end of the processing for address generation need to be controlled in addition to controlling the processing for base address generation. A timing control unit manages control for address conversion on a clock cycle basis. The difference between the processing speed in the address generation processors and the processing speed in the address conversion circuit is absorbed by buffers.
Claims16
1-28. (canceled)
An address generation apparatus for an array processor, the apparatus being connected to a plurality of data storage units for storing data and to an array computing device that receives data from the plurality of data storage units to perform computation thereon, the apparatus comprising:
- a base address generation unit that generates a base address for an address issued to the data storage unit;
- a plurality of base address storage units that temporarily store the base address obtained from the base address generation unit;
- an address computing unit that performs preset address computation on the base address stored in the base address storage unit;
- an address transfer unit that transfers the address obtained from the address computing unit to an associated one of the data storage units;
- and
- a timing control unit that controls the timing of execution of the address computation by the address computing unit.
A method for address generation for an array processor, the array processor including a plurality of data storage units and an array computing device that receives data from the plurality of the data storage units to execute computation thereon, the method comprising:
- generating a base address for an address issued to the data storage unit;
- temporarily storing the base address in a base address storage unit;
- an address computation unit executing preset address computation on the base address stored in the base address storage unit;
- transferring the address resulting from the address computation to an associated one of the data storage units;
- and
- a timing control unit controlling the timing of execution of the address computation by the address computation unit.
Dependencies are inferred from the claim text.