Detecting lost and out of order posted write packets in a peripheral component interconnect (pci) express network

A system for processing packets in a PCIe network, the system comprising:

• a receiver in communication with a PCIe switch for receiving a PCIe posted write packet, the PCIe posted write packet including a received tag identifier and a requesting device identifier identifying a requesting device;
• a storage mechanism for storing an expected tag identifier for the requesting device;
• a comparator for comparing the received tag identifier to the expected tag identifier and setting an error flag in response to the received tag identifier not matching the expected tag identifier.

A system for processing packets in a PCIe network, the system comprising:

• a posted write packet mechanism at a requesting device for accessing a PCIe posted write packet that identifies a receiving device and for inserting a current tag identifier corresponding to the receiving device into a tag field in the posted write packet;
• a storage mechanism at the requesting device for storing the current tag identifier corresponding to the receiving device;
• a transmitter at the requesting device in communication with a PCIe switch for transmitting the PCIe posted write packet to the receiving device via the PCIe switch.