Gate driver having an output enable control circuit

A gate driver, comprising:

• a shift register, for generating a plurality of scan signals according to a vertical synchronous signal and a vertical clock signal;
• an output enable control circuit, for generating a second output enable signal according to the vertical synchronous signal, the vertical clock signal and an output enable signal, when the vertical synchronous signal and the vertical clock signal are both triggered together for two times, the second output enable signal converting from the high voltage level to a low voltage level;
• and
• a logic control circuit, electrically connected to the shift register and the output enable control circuit, for outputting the plurality of the scan signals when the second output enable signal is at the low voltage level.